In standard dynamic random access memories (DRAMs), there are two portions to the address which are received sequentially. A row address is followed by a column address. The DRAM receives a row address strobe (*RAS) at a logic low to indicate that the row address is valid. Some time later the column address is valid. The column address can either be clocked by a column address signal (*CAS) switching to a logic low or by a predetermined delay following signal *RAS switching to a logic low. After signal *RAS switches to a logic low, the DRAM latches data along a selected row in sense amplifiers at the ends of the columns. The column address then determines which column provides the data as the output.
In order to provide data at a faster rate, modes of operation have been developed to take advantage of the data that is latched in response to the row address. One way this is achieved is by sequentially providing column addresses without any intervening row address. The DRAM knows that it is receiving column addresses only by signal *RAS being held to a logic low. There are two techniques for providing data to column only addresses. A clocked static column mode responds to the column address upon signal *CAS switching to a logic low and then outputs the corresponding data a predetermined delay time following signal *CAS switching to a logic low. A transparent static column mode DRAM continuously responds to the address as a column address and provides the data in response to signal *CAS switching to a logic low so that signal *CAS is used merely as an output enable signal.
Both of these modes provide for improved speed over a normal cycle because there is no row address cycle. The limitation, however, is that of the number of column address signals. The amount of latched data may in fact be greater than the selection available from the column address alone. For example, in the case of a 1 megabit (1,048,576 bits) DRAM, there are 2 sets of 10 address bits sequentially received. Each set can perform a one of 1024 selection. Consequently, the 10 bit column address can only select from 1024 bits of data. There may, however be more than 1024 bits of data that are latched. This is particularly true in a 1 megabit DRAM that must meet a 512 cycle refresh specification. To meet a 512 cycle refresh requirement, the DRAM must refresh every memory location with 512 row cycles. In order to achieve a 512 cycle refresh, 2048 memory locations must be refeshed for each unique row address. This implies that 2048 bits of data are latched for each unique row address. One of the bits in the row address is used to define which latch location is output as data. There are thus 2048 bits of latched data which are available for rapid output. The 10 column address bits, however, can only define 1024 locations.